Principles of Secure Processor Architecture Design
Jakub Szefer, assistant professor of electrical engineering and of computer science
(Morgan & Claypool Publishers)
With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today’s processors has recently increased. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today.
This book provides insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).
“Principles of Secure Processor Architecture Design” presents the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It educates readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. It details the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, it presents numerous design suggestions, as well as discussing pitfalls and fallacies that designers should avoid.